The present invention relates generally to the field of processors and in particular to a method of reducing power consumption in a processor by suppressing TLB accesses for intra-page branches where the branch target address can be determined from the branch instruction address or the branch instruction itself.
Portable electronic devices have become ubiquitous accoutrements to modern life. Two relentless trends in portable electronic devices are increased functionality and decreased size. Increased functionality demands increased computing power—in particular, ever faster and more powerful processors.
As well as providing advanced features and functionality that require faster processors, portable electronic devices themselves continue to shrink in size and weight. A major impact of this trend is the decreasing size of batteries used to power the processor and other electronics in the device. While advances in battery technology partially offset the problem, the decreasing size of batteries imposes a requirement to decrease the power budget in portable electronic device electronics, and in particular to decrease the power used by the processor.
Accordingly, processor improvements that increase performance and/or decrease power consumption are desirable for many applications such as portable electronic devices. Modern processors commonly employ a memory hierarchy that places small amounts of fast, expensive memory close to the processor, backed up by large amounts of slower, inexpensive memory somewhat more distant from the processor. A large main memory is commonly divided into logical units called pages. All data or instructions within a page commonly have the same attributes, which define common characteristics, limit access via permissions, and the like. The page attributes are typically stored in a Translation Lookaside Buffer (TLB). In general, for every instruction fetch, the processor should pass the instruction address through the TLB to verify that the program has permission to access and execute the instruction.
Checking attributes such as permissions in the TLB consumes power. Since each instruction on a page has the same attributes and hence the same permissions, once any instruction on the page is verified through the TLB, all other instructions on the same page may be fetched without checking TLB attributes. For example, it is known in the art to bypass a TLB attribute check for instructions executed sequentially to a previously checked instruction, until the sequential instructions cross a page boundary.
It would similarly be advantageous to bypass the TLB attribute check for branch targets that do not leave a page. The branch target address calculation and the selection of the branch target address from which to fetch the next instruction is typically the critical path of a branch instruction, and a limiting factor in determining the machine cycle time. A TLB attribute check of the branch target address may be avoided if the target address is in the same page as the instruction address. However, comparing the branch target address to the address that was last checked by the TLB to determine if the branch target address is with the same page as the last address check by the TLB may lengthen the cycle time by adding delay to a critical path. Additionally, since the calculation must be performed each time the branch instruction executes, the extra power consumed for the calculation would offset the power consumption gained from bypassing the TLB attribute checks for target and instruction addresses determined to be on the same page.